Verilog `ifdef equivalent in VHDL

Hi Tricky

What I'm missing in the "--synthesis translate_off " statement is that it is not conditional.

It's great if you have a bit of code that you wish to omit under some condition (synthesis verses simulation), but what happens if you want to replace a part of your design with something else?

For example lets say I wish to instantiate a DFF instead of SRFF,

In that case I will have to define the pins for the SRFF even when I'm using the generate statement for instantiating only the DFF.

I can use the same pin names for both components, but for large designs it's confusing, and then you have width mismatch etc.