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Altera_Forum
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14 years ago

Verilog `ifdef equivalent in VHDL

Hi I've just learned that in Verilog you can use an `ifdef statement that makes Quartus ignore the following code (until the next`endif) you can define a macro in the qsf file (or through the...
Altera_Forum's avatar
Altera_Forum
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14 years ago

there is the option for:

--synthesis translate_off

any code here is ignored for synthesis, but will still run in a simulator.

--synthesis translate_on

While this is greate for simulation only processes and the like, it doesnt quite do what you want. The only way to do what you want is with generates.