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Junyong's avatar
Junyong
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Verilog HDL Modeul instantiation error

Hello all, I'm trying to compile "Stratix 10-Tx PAM4 2x51 Gbps with SMA Design Example 18.1" with my Strati10 Tx Signal Integrity Dev Kit. I got an error message below during compilation: Error(1...
Hdl
  • FvM's avatar
    FvM
    3 years ago
    Hi,
    guess you are using a newer version than Quartus 18.1? The example design built with 18.1 will probably need IP regeneration or even some modifications to work with newer Quartus versions. Problems of this kind have been frequently reported.
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

For example design, you are encouraged to use same version as mentioned to avoid expected issue e.g. IP upgrades and compatibility.

Use different version is at your own responsibility.

May revert to 18.1 per mentioned.


Junyong's avatar
Junyong
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Yes. After matching Quartus version to the example file, it was effective.

I faced another issue, but the issue I addressed was resolved.

Thank you very much for your help.

Best Regards,

Junyong