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Altera_Forum's avatar
Altera_Forum
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9 years ago

verilog HDL error :constant expression cannot contain a hierarchical identifier

Hello everyone!

I got an error message while synthesizing my code in Quartus Prime, it said:

verilog HDL error : constant expression cannot contain a hierarchical identifier.

The example code is : 


interface m_if#(
    parameter LEFTPARA_BITW,
    parameter RIGHTPARA_BITW,
    parameter RESULT_BITW
) (
    input bit clk,
    input wire rst
);
    logic leftpara;
    logic rightpara;
    logic res;
    modport port(input clk, rst, leftpara, rightpara, output res);
endinterface
module tb_m(
    m_if.port p
);
    localparam tmp_resbitw = p.LEFTPARA_BITW > p.RIGHTPARA_BITW ? p.LEFTPARA_BITW : p.RIGHTPARA_BITW;// synthesizer reports error message like above.
    wire tmpres = (tmp_resbitw)'(p.leftpara) + (tmp_resbitw)'(p.rightpara);
    always_comb begin
        if (p.RESULT_BITW > tmp_resbitw) p.res = (p.RESULT_BITW)'(tmpres);// synthesizer reports error message like above.
        else                                           p.res = tmpres;
    end
endmodule

For I want to use the parameter in module 'tb_m' which is defined in interface 'm_if', how can I work around it?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    This is legal and works in simulation. I suspect it is not yet supported in Quartus Synthesis tools.

    I suspect you are writing this from VHDL. But all you have to do is write 

    
module tb_m(
    m_if.port p
);
    always_comb begin
        p.res = {pleftpa + p.rightpa};
endmodule

    Putting the addition + inside a concatenation {} makes the intermediate result with of addition self-determined, so its length is MAX(L(leftpa), L(rightpa)). See table 11-21 in the 1800-2012 LRM. There's no need to truncate the intermediate result width if it is larger than the final result. Verilog does that silently for you.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    This is legal and works in simulation. I suspect it is not yet supported in Quartus Synthesis tools.

    I suspect you are writing this from VHDL. But all you have to do is write 

    
module tb_m(
    m_if.port p
);
    always_comb begin
        p.res = {pleftpa + p.rightpa};
endmodule

    Putting the addition + inside a concatenation {} makes the intermediate result with of addition self-determined, so its length is MAX(L(leftpa), L(rightpa)). See table 11-21 in the 1800-2012 LRM. There's no need to truncate the intermediate result width if it is larger than the final result. Verilog does that silently for you.

    --- Quote End ---

    Hi, Mr.dave_59!

    Thank you for replying.

    Does Altera provide any way for us to commit these deficiency?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    Hi, Mr.dave_59!

    Thank you for replying.

    Does Altera provide any way for us to commit these deficiency?

    --- Quote End ---

    Yes. Open a service request. You'll need an Altera account to do that.