verilog HDL error :constant expression cannot contain a hierarchical identifier

This is legal and works in simulation. I suspect it is not yet supported in Quartus Synthesis tools.

I suspect you are writing this from VHDL. But all you have to do is write

module tb_m(
    m_if.port p
);
    always_comb begin
        p.res = {pleftpa + p.rightpa};
endmodule

Putting the addition + inside a concatenation {} makes the intermediate result with of addition self-determined, so its length is MAX(L(leftpa), L(rightpa)). See table 11-21 in the 1800-2012 LRM. There's no need to truncate the intermediate result width if it is larger than the final result. Verilog does that silently for you.