Verilog file not automatically generated by the SOPC builer in quartus II

Hello,

I am new to working with FPGA and am using an ALTERA DEO NANO Cyclone IV E development board. I was following the steps of the DEO NANO user manual v1.7 for making a Nios II project. And in the step where it says to click the generate button in the sopc builder a verilog file is not automatically created. Therefore I cannot go to the next steps. And even though it says the "system generation was successful" in the end it displays the below Information beforehand? I checked and rechecked the steps I followed but couldn't come up with a solution.

Info: Wrote C:/Users/Documents/Altera (FPGA)/db/DEO_NANO_SOPC.sopcinfo

Info: DEO_NANO_SOPC: Wrote C:\Users\Documents\Altera (FPGA)\db/DEO_NANO_SOPC.html

Info: DEO_NANO_SOPC: Generating QIP file.

Info: Starting PTF file elaboration.

/usr/bin/sh: -c: line 0: syntax error near unexpected token `('

/usr/bin/sh: -c: line 0: `. H:/altera/10.1/quartus/sopc_builder/bin/nios_sh ; H:/altera/10.1/quartus/sopc_builder/bin/sopc_builder --classic --no_splash --refresh C:/Users/Documents/Altera\ (FPGA)/db/DEO_NANO_SOPC.ptf'

Info: Finished elaborating PTF file.

Executing: H:/altera/10.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/Documents/Altera (FPGA)/db/DEO_NANO_SOPC.ptf

Info: Starting generation...

/usr/bin/sh: -c: line 0: syntax error near unexpected token `('

/usr/bin/sh: -c: line 0: `. H:/altera/10.1/quartus/sopc_builder/bin/nios_sh ; H:/altera/10.1/quartus/sopc_builder/bin/sopc_builder --classic --generate C:/Users/Documents/Altera\ (FPGA)/db/DEO_NANO_SOPC.ptf'

Info: System generation was successful.

Can anyone tell me how I should proceed in order to complete the project?