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Altera_Forum
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10 years ago

Verilog file not automatically generated by the SOPC builer in quartus II

Hello, I am new to working with FPGA and am using an ALTERA DEO NANO Cyclone IV E development board. I was following the steps of the DEO NANO user manual v1.7 for making a Nios II project. And...
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Altera_Forum
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10 years ago

The Altera tools can't deal with spaces or () anywhere in the path. You need to delete this project and start again with a path other than Altera (FPGA). Altera-FPGA would work fine. Renaming the directory may or may not work.