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Altera_Forum
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10 years ago

Verilog file not automatically generated by the SOPC builer in quartus II

Hello, I am new to working with FPGA and am using an ALTERA DEO NANO Cyclone IV E development board. I was following the steps of the DEO NANO user manual v1.7 for making a Nios II project. And...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I'd recommend starting with the example in the My_First_NiosII_Qsys.pdf file. Qsys is the replacement for SOPC builder which is now out of date. Qsys is easier to use as well. You may need to download the latest CD zip file for the DE0 nano board. The QSYS project may not be on the CD shipped with the board. Make sure you download the latest Quartus software as well.