Verilog excess Three no out puts

Case statements are better than if's if you have more than just a few cases. IE for 1-3 statements, it's if's are fine, but for more than 3 or 4 branches, a case statement is better.

If then elses, are always priority logic. IE the first condition is the most likely to occur. With case statements, you have the options of using synthesis "pragmas" that allows the tool to reduce the logic required. This allows the logic to run faster and be smaller, but at the cost that the simulator may not simulate the design exactly anymore.

The two most commonly used pragmas are parallel_case and full_case. Where parallel_case treats all cases as having the same priority, so the normal top-down priority (if, then, else) style conditioning is removed. full_case is telling the tool there is no other cases possible. It reduces the decoder required for each of the valid cases, but if a case that wasn't defined appears in the logic, it may activate multiple case branches.

Look up these pragmas, and read about them. They are very useful, but also can cause problems if not used properly.

Pete