Verilog excess Three no out puts

You have a couple of issues going on.

In the test bench. W is changing but not clock. So you only get one clock edge per group of W. Is this what you intended?

In the source code:

R is never set, and since only 1 positive clock edge occurs, not all bits are configured.

Add R=4'd0;

right after the begin and before the case(state) statement.

the second issue is the structure of your case statement: You have:

Start:      NextState = (W==1)? CarryOne:NoCarryOne;
Start:	R=(W==1)? 1'b1:1'b1;

The second "Start" statement never is get ran, since it matches the first one and drops out. This needs to be written as:

Start:      begin
                  NextState = (W==1)? CarryOne:NoCarryOne;
                  R=(W==1)? 1'b1:1'b1;
              end

for all your case structure.

so the finished code should look like:

`timescale 1ns/ 1ns
module excess_three (W,R,clk,Reset);
input W;
input clk;
input Reset;
output  R;
reg R;
reg  State;
reg  NextState;
parameter  Start = 3'b000 ,CarryOne= 3'b101, NoCarryOne= 3'b001;
parameter  CarryTwo= 3'b011, NoCarryTwo= 3'b111;
parameter  CarryThree= 3'b010, NoCarryThree= 3'b110;
always @ (W or State)
begin
  R=4'd0;
  case (State)
    Start:      begin
                   NextState = (W==1)? CarryOne:NoCarryOne;
                   R=(W==1)? 1'b1:1'b1;
                end
    CarryOne:   begin
                   NextState = (W==1)? CarryTwo:CarryTwo;
                   R=(W==1)? 1'b1:1'b0;
                end
    NoCarryOne: begin
                   NextState = (W==1)? CarryTwo:NoCarryTwo;
                   R=(W==1)? 1'b0:1'b1;
                end
    CarryTwo:  begin
                  NextState = (W==1)? CarryThree:NoCarryThree;
                  R=(W==1)? 1'b0:1'b1;
               end
    NoCarryTwo:begin
                  NextState = (W==1)? NoCarryThree:NoCarryThree;
                  R=(W==1)? 1'b1:1'b0;
               end
   CarryThree: begin
                  NextState = (W==1)? NoCarryThree:3'bxxx;
                  R=(W==1)? 1'b1:1'b0;
               end
  NoCarryThree:begin
                  NextState = (W==1)? Start:Start;
                  R=(W==1)? 1'b1:1'b0;
               end
endcase
end
always @ (posedge clk or negedge Reset)
begin
    if (Reset==0)
        State <= Start;
     else
        State <=NextState;
end
endmodule