Verilog Compiler Differences Quartus / ModelSim

Hello,

I am not very experienced with HDLs.

I am experienced with C, C++, non-procedural languages, logic design, IC design.

I do understand that Verilog is not fundamentally procedural, and I do understand the difference between Simulateable and Sythesizable.

I am finding differences between the way that Quartus and ModelSim interpret my Verilog. I can get either one to work (albiet a little differently), but not both on the same code.

Code Snippets:

-----------------------------------------

module Ram_Definition( clk, ...etc.....);

parameter ADDRESS_BITS=5;

parameter DATA_BITS=2;

input clk;

......etc.........

reg [DATA_BITS-1:0] mem [(1<<ADDRESS_BITS)-1:0];

.........etc........

------------------------------------------------------

module Thing(....etc....)

Ram_Definition# (.ADDRESS_BITS (5), .DATA_BITS(2))

ram1(.clk (clk), ....etc......);

Ram_Definition ram2(.clk (clk), ......etc......)

initial begin

ram1.mem[16]=2'b00;

end

......etc.......

--------------------------------------------------------

The above works for ModelSim, and sets ram1.mem[16] to 00, ram2.mem[16] is still xx. This seems correct. Quartus chokes on this.

Quartus, instead of ram1.mem[16]=2'b00, wants Ram_Definition.mem[16]=2'b00, and sets both ram1.mem[16] and ram2.mem[16] to 00. ModelSim chokes on this.

I have read various texts on Verilog, but have yet to find a formal definition which would cover which of these behaviours is correct, but they are plainly different.

Can anyone please explain what I am doing wrong?

Thanks,

Paul Hilton

p.s.

Other differences occur when trying to use $readmemb, which works in ModelSim, and Quartus accepts but doesn't actually load the memory (When I run the real hardware).

Is it possible that this has something to do with it not actually using RAM for the arrays mem in Ram_Definition?

Other differences occur when trying to use parameters not yet declared,

e.g.

------------------------------------------------

module Ram_Definition(

input clk,

input [ADDRESS_BITS-1:0] write_address,

.......etc........

);

parameter ADDRESS_BITS=5;

.......etc........

-------------------------------------------------

which ModelSim accepts, but not Quartus. (Hence I used the separate name list and type definitions.)