Verilog code for sine pulse width modulation

Thanks FvM.. You please go through my code once.. There i have used cordic algon for sine generation (i found it on internet), please tell whether it is correct or not.. And in that sine wave code how to change the amplitude and frequency.. And for triangle (or ramp) generation, i have used counter, you please check that code also.. In my logic counter will increase in steps of 1 with clock frequency, after it is reaching to particular peak it will decrease.. That peak will decide the frequency of triangle.. Suppose my clock freq=50Mhz, and i want 10Khz triangle, then the peak is (50M/10K = 5000). I am thinking like this, please tell me if i am wrong. So please check my code which i have attached and tell the modification. This forum is my only hope, my supervisor is not helping.. please...