Verilog code for sine pulse width modulation

The sine generator is very simple Cordic implementation known to work, but the ramp generator is scrap. Check it's operation with pencil and paper method or in a simulation. You need at least an up_down state variable. As shown, it will only count one step back and forth.

You also need to scale either sine or ramp signal. Now you are comparing 16 bit ramp (13.2 Bit utilized) with 8 Bit sine range.

Finally, a signed variable must be declared as such in Verilog, all variables are unsigned by default.