Verilog code for memory simulating but not giving output in quartusII

i simulated a verilog code for memory controller in modelsim and it is working fine.But when tested in quartusII 7.2 it simulates but it does not give the desired output as shown in modelsimPE 6.1c.It does not pass the read write signals in quartus.

I'm posting the code below.Plzzzzzzz help.

Verilog code

module main(data_out,iowriteoutput,addr,clock,enable);

input clock,enable;

input[7:0] iowriteoutput;

input [7:0] addr;

output [7:0] data_out;

wire read,write;

control M1(read,write);

mem M2(data_out,clock,enable,read,write,addr,iowriteoutput);

endmodule

module control(read,write);

output reg read,write;

integer i;

initial begin

read=0;

write=0;

for(i=0;i<64;i=i+1)

begin

write=1;

# 10write=0;

read=1;

# 10read=0;

end

end

endmodule

module mem(data_out,clock,enable,read,write,addr,iowriteoutput);

input clock,enable,read,write;

input[7:0] iowriteoutput;

output [7:0] data_out;

reg[7:0] data_out;

input [7:0] addr;

reg[7:0]tmp[63:0];

always@(posedge clock)

begin

if(enable==1'b1)begin

if(read==1)begin

data_out<=tmp[addr];

end

else if(write==1)begin

tmp[addr]<=iowriteoutput;

end

else begin

data_out<=8'b00000000;

end

end

end

endmodule