Verilog bug, DE2-70 board

You need to write a testbench and simulate your code so you can see what's going on.

I wrote this following your instructions and I can't get it to work in either case.

`timescale 1 us/1ns

module lab4_tb;

wire [17:0] SW = 18'h1;

reg [3:0] KEY;

wire [7:0] HEX0;

wire [7:0] HEX1;

wire [7:0] HEX2;

wire [7:0] HEX3;

wire [7:0] HEX4;

wire [7:0] HEX5;

wire [7:0] HEX6;

wire [7:0] HEX7;

lab4 uut (SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);

integer i;

initial begin

KEY <= 4'h0;

for(i = 0; i < 100; i = i+1) begin

# 10; KEY[3] <= 1'b1;# 1 KEY[3] <= 1'b0;

end

end

endmodule