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frank2597's avatar
frank2597
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Verilog: Attempting to make a signal high for 5 clock cycles and then remain low

Hello, I am trying to make the signal called ld_tx_data_scope a value of 1 after the first 5 positive edges and remain high for 5 positive edges and then have it go low and stay low. However, simula...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,

    Because you haven't initialize the reg ld_tx_toggle. If you had initialized like this reg ld_tx_toggle = 1'b0; You'll get correct simulation like pic below:

    Thanks,

    Best regards,

    Sheng

    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.

roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
3 years ago

Hi Frank,

There are numerous problems in your Verilog code, but this is not an appropriate place for this query. This forum is meant for discussions on issues pertaining to Quartus software. The problems you're having are with basic Verilog programming, having nothing to do with Quartus in particular. I'd suggest you begin with a good primer course or book to learn the fundamentals of RTL design and the Verilog language.

-Roee