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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Verilog always blocks

Hi all,

So I'm a verilog beginner having just picked myself up a DE1 board to play with. Currently I am having issues with always blocks. Given this simple example: 


module FirstProject (SW, LEDR);
    input  SW;
    output  LEDR;
    
    reg  LEDR;
    reg  counter = 3'b0;
    
always (SW) //at symbol removed as forum thinks I'm trying to post a link
begin
    counter = (counter + 1)% 4'b1000;
    LEDR = counter;
end
endmodule

My understanding is that the always block should only execute when a change in SW[0] occurs, but on the board the always block is continually executed resulting in all 3 LED's being lit.

If I change always (at) (SW[0])

to always (at) (posedge SW[0]) then things behave as expected and the LED's count upwards when the switch is toggled on.

So my question is why would the not behave as expected and only change each time the switch is toggled?

Any help would be appreciated.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Your question is quite right and actually indicates the misleading and poor description given around about otherwise powerful tools.

    without posedge you are asking to have a counter that counts up without any waiting except for change of sw (which is not read in the block anyway and becomes only a simulation feature i.e. the actual hardware will ignore your condition of change of sw and will not build any logic connection to sw(as far as I know). There will be no register even though you declare a register, instead the design will latch the count value) so it is really always just a counter counting up at full silicon speed. with clock edge you are asking to build an actual wait for signal change and this translates to a clocked register waiting for your finger.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Would really recommend looking at the concepts of RTL coding. HDL languages like Verilog, VHDL need to be used in an RTL style of coding so that your design can be implemented in terms of gates & flops (LUTs for FPGAs). For this, there are coding guidelines to be followed when trying to infer different types of logic; these guidelines differ (slightly) from vendor to vendor.

    Have a look at Altera's recommended coding styles in the below link:

    http://www.altera.com/literature/hb/qts/qts_qii51007.pdf
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I would recommend something like this instead: 

    
always @ (posedge clk or posedge reset)
begin
  if (reset == 1)
  begin
    counter <= 0;
  end
  else if (SW == 1)
  begin
    counter <= counter + 1;   // assuming you want a counter that goes from 0 to 7 here, otherwise you would code this differently
  end
end
assign LEDR = counter;  // make LEDR a wire instead of a reg