Verilog always blocks

Your question is quite right and actually indicates the misleading and poor description given around about otherwise powerful tools.

without posedge you are asking to have a counter that counts up without any waiting except for change of sw (which is not read in the block anyway and becomes only a simulation feature i.e. the actual hardware will ignore your condition of change of sw and will not build any logic connection to sw(as far as I know). There will be no register even though you declare a register, instead the design will latch the count value) so it is really always just a counter counting up at full silicon speed. with clock edge you are asking to build an actual wait for signal change and this translates to a clocked register waiting for your finger.