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Altera_Forum
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13 years ago

Verilog always blocks

Hi all, So I'm a verilog beginner having just picked myself up a DE1 board to play with. Currently I am having issues with always blocks. Given this simple example: module FirstProjec...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Would really recommend looking at the concepts of RTL coding. HDL languages like Verilog, VHDL need to be used in an RTL style of coding so that your design can be implemented in terms of gates & flops (LUTs for FPGAs). For this, there are coding guidelines to be followed when trying to infer different types of logic; these guidelines differ (slightly) from vendor to vendor.

Have a look at Altera's recommended coding styles in the below link:

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf