Verilog | Instantiating a varied parameter

Hi Galfonz,

Thank you for your reply.

What do you mean by "You can do calculations with them"?

I saw that in System Verilog one can use something which is called 'parameter type' - is it related to my question?

Anyways, here is my code for calculating 1's in an input vector:

`resetall

`timescale 1ns/10ps

`define CCT 10

module ones_counter

// Port Declarations

(input wire aclr_n,

input wire clk,

input wire [15:0] data,

input wire sync_n,

input wire fin_read,

output reg [2:0] ones_num

);

// Internal Declarations

wire equ;

reg [7:0] data_shift;

reg [2:0] ones_cnt;

/* ---------------------------------------------------------------------------

****************** counting number of ones in a vector ***********************

--------------------------------------------------------------------------- */

always @ (posedge clk, negedge aclr_n)

begin

if (!aclr_n)

data_shift <= 8'b0;

else

if (sync_n)

data_shift <= data[13:6];

else

data_shift <= data_shift << 1;

end

assign equ = (data_shift[7] ^ 1'b0) & (!sync_n);

always @ (posedge clk, negedge aclr_n)

begin

if (!aclr_n)

ones_cnt <= 3'b0;

else

if (equ && data[15])

ones_cnt <= ones_cnt + 1'b1;

else

if (fin_read)

ones_cnt <= 3'b0;

end

always @ (posedge clk, aclr_n)

begin

if (!aclr_n)

ones_num <= 3'b0;

else

if (data_shift[7:0] == 8'b0)

ones_num <= ones_cnt;

else

ones_num <= 3'b0;

end

endmodule

I wish to instantiate ones_num register value to my main code.

- refael.