Vdh: can't determine definition of operator ""-"" -- found 0 possible definitions

Hello,

My code is the following and I have this error: can't determine definition of operator ""-"" -- found 0 possible definitions. The error is in this line:

W(i,j)<=2.25 -(EE(i,j));

At first, instead of using "SIGNED" I had determined all the inputs, output, arrays and variables as STD_LOGIC_VECTOR but I had the same error

so I changed them but the error has not bee repaired.

Why this error is appeared?What I have to change?Thank you very much in advance..

LIBRARY ieee;

USE ieee.std_logic_1164.all;

--USE ieee.std_logic_arith.all;

--USE ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

USE ieee.std_logic_signed.all;

ENTITY multiplier IS

GENERIC ( bits: INTEGER := 5; --# of bits per word

words: INTEGER := 25); --# of words in the memory

PORT ( clock:IN STD_LOGIC;

z:IN SIGNED(2 DOWNTO 0) :="001";

b:OUT SIGNED(7 DOWNTO 0));

END multiplier;

ARCHITECTURE behavior OF multiplier IS

TYPE vector_array IS ARRAY (1 TO bits, 1 TO bits) OF SIGNED(3 DOWNTO 0);

TYPE vector_array2 IS ARRAY (1 TO bits, 1 TO bits) OF SIGNED(7 DOWNTO 0);

SIGNAL memory: vector_array := (("0000", "0001", "0000","0000","0000"),

("0000", "0000", "0001","0000","0000"),

("0001", "0001", "0001","0000","0000"),

("0000", "0000", "0000","0000","0000"),

("0000", "0000", "0000","0000","0000"));

SIGNAL N : vector_array ;

SIGNAL X : vector_array ;

SIGNAL EE : vector_array2 ;

SIGNAL W : vector_array2 ;

BEGIN

PROCESS(clock,memory,N)

CONSTANT k : INTEGER:=1;

CONSTANT m : INTEGER:=5;

VARIABLE l : SIGNED(3 DOWNTO 0);

VARIABLE r : SIGNED(3 DOWNTO 0);

VARIABLE t : SIGNED(3 DOWNTO 0);

VARIABLE d : SIGNED(3 DOWNTO 0);

VARIABLE e : SIGNED(3 DOWNTO 0);

VARIABLE f : SIGNED(3 DOWNTO 0);

VARIABLE g : SIGNED(3 DOWNTO 0);

VARIABLE h : SIGNED(3 DOWNTO 0);

BEGIN

FOR i IN 1 TO 5 LOOP

FOR j IN 1 TO 5 LOOP

IF(i=k AND j=k) THEN

l:=memory(i,m);

r:=memory(i,j+1);

t:=memory(m,j);

d:=memory(i+1,j);

e:=memory(m,m);

f:=memory(m,j+1);

g:=memory(i+1,j+1);

h:=memory(i+1,m);

ELSIF(i=k AND (j>k AND j<m)) THEN

l:=memory(i,j-1);

r:=memory(i,j+1);

t:=memory(m,j);

d:=memory(i+1,j);

e:=memory(m,j-1);

f:=memory(m,j+1);

g:=memory(i+1,j+1);

h:=memory(i+1,j-1);

ELSIF(i=k AND j=m) THEN

l:=memory(i,j-1);

r:=memory(i,k);

t:=memory(m,j);

d:=memory(i+1,j);

e:=memory(m,j-1);

f:=memory(m,k);

g:=memory(i+1,k);

h:=memory(i+1,j-1);

ELSIF((i>1 AND i<m) AND j=k) THEN

l:=memory(i,m);

r:=memory(i,j+1);

t:=memory(i-1,j);

d:=memory(i+1,j);

e:=memory(i-1,m);

f:=memory(i-1,j+1);

g:=memory(i+1,j+1);

h:=memory(i+1,m);

ELSIF(i=m AND j=k) THEN

l:=memory(i,m);

r:=memory(i,j+1);

t:=memory(i-1,j);

d:=memory(k,j);

e:=memory(i-1,m);

f:=memory(i-1,j+1);

g:=memory(k,j+1);

h:=memory(k,m);

ELSIF(i=m AND (j>k AND j<m)) THEN

l:=memory(i,j-1);

r:=memory(i,j+1);

t:=memory(i-1,j);

d:=memory(k,j);

e:=memory(i-1,j-1);

f:=memory(i-1,j+1);

g:=memory(k,j+1);

h:=memory(k,j-1);

ELSIF(i=m AND j=m) THEN

l:=memory(i,j-1);

r:=memory(i,k);

t:=memory(i-1,j);

d:=memory(k,j);

e:=memory(i-1,j-1);

f:=memory(i-1,k);

g:=memory(k,1);

h:=memory(k,j-1);

ELSIF((i>1 AND i<m) AND j=m) THEN

l:=memory(i,j-1);

r:=memory(i,k);

t:=memory(i-1,j);

d:=memory(i+1,j);

e:=memory(i-1,j-1);

f:=memory(i-1,k);

g:=memory(i+1,k);

h:=memory(i+1,j-1);

ELSE

l:=memory(i,j-1);

r:=memory(i,j+1);

t:=memory(i-1,j);

d:=memory(i+1,j);

e:=memory(i-1,j-1);

f:=memory(i-1,j+1);

g:=memory(i+1,j+1);

h:=memory(i+1,j-1);

END IF;

N(i,j)<= (l+r+t+d+e+f+g+h);

X(i,j) <= memory(i,j)+(N(i,j)+N(i,j));

EE(i,j)<=(X(i,j)-6)*(X(i,j)-6);

W(i,j)<=2.25 -(EE(i,j));

END LOOP;

END LOOP;

FOR i IN 1 TO 5 LOOP

IF(z=i) THEN

b<=EE(i,i);

END IF;

END LOOP;

END process;

END behavior;