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Altera_Forum's avatar
Altera_Forum
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13 years ago

VCD file generation in Modelsim: Problem with internal signals

Does VCD file created in Modelsim capture the internal signal activities in the design hierarchy..? or does it capture the signal activities of only the I/O signals..?

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  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yes capture internal signals, make sure you have clock period right for PLL to lock