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Altera_Forum
Honored Contributor
Honored ContributorVCD file generation in Modelsim: Problem with internal signals
Does VCD file created in Modelsim capture the internal signal activities in the design hierarchy..? or does it capture the signal activities of only the I/O signals..?
Altera_ForumHonored Contributor
Honored ContributorYes capture internal signals, make sure you have clock period right for PLL to lock
