variable initialization help

Many thanks for your help!

For the example I have above, where to initialize the signal v1?

ENTITY example IS
PORT (
   clk : IN STD_LOGIC;
   initval : IN INTEGER;
   ...
);
END ENTITY;
ARCHITECTURE rt OF example IS
   SIGNAL v1 : INTEGER := initval; ------------------------- If I initialized here
...
   ex: PROCESS (clk)
   BEGIN
      IF (rising_edge(clk)) THEN
         IF (v1 < 100) THEN
            v1 <= v1 + 1;
         END IF;
      END IF;
   END PROCESS;
END ARCHITECTURE;

If I initialized there, suppose I input 1 on port initval at clock edge 1, and the v1 will keep increase until 100 at every clock edge. However, if I input a new value at some other clock edge, how does this will effect the process?