Using vho file with cadence tools

ok, I 've tried the example from altera and it seems to work well... ( multiplier ) They are using verilog model, so I have compiledmy design another time to generate a verilog output( .vo) and created a verilog testbench, but no way I can make working the PLL...

Did anyboby have tried this before?

Maybe the PLL behaviour has a issue... need some help!

OK, solved!

In fact the input frequency of my PLL was too low for it to work. With the PLL file from quartus compiled with ncvhdl it works fine, even when the quartus libraries are compiled with ncvhdl, this make a uge difference!

So I always should use the .vho files generated by quartus, otherwise the funcionnal behaviour will be wrong (maybe right just because I simulated analog blocks). THis is a very nice feature from quartus I must say.

Great.

ok, I go for a coffee now,

hope it will help someone!

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Hello,

I am running into problems while trying to simulate a very simple design ( the design just consist of a vhd file generated by quartus to use a simple PLL ( one clock input, one clock output) ) to have some insights about how to simulate a design compiled with quartusII into the cadence tools.

Here is the situation:I am using cadence tools, and I wanted to see the behaviour of a PLL using the .vho file generated by quartusII.

I have compiled and elaborated it using ncvhdl and ncelab, (by the way, no problem to compile the library altera_mf and stratixii ).

When I simulate it a get no clock coming out of the PLL.

Then I changed the .vho by .vhd ( the design just contain one file, the one generated by quartus ) and the simulation works ( I get a clock out of the pll ).

I do not understand why the .vho file, so the .vhd file compiled with quartus differs from the compilation with ncvhdl ( a mean in a functional behaviour ). Any tips to know what's going on and how I could solve this problem?

I need to understand it to be able to simulate a much bigger design within ncsim... I'd like to use the vho file in my simulation to be absolutly sure of what I load in my device.

Tell me if you missed something here!

Thank you

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Yes, I have run into the same problems. we use Incisive simulation using scripts. It appears that using Quartus's MegaWizard .vho is a HIT or MISS operation. For example, I have the NCO. Nothing more. In order to simulate the NCO the .vho file had to be compilied by the Incisive simulator. However, another project was made and simply had just a PLL, like yours. This time using the .vho failed. So I used the .vhd and it simulated.

Altera really makes is confusing and apparently don't have a standard. They should have just one standard. If you have an IP core then to simulated it you use the .vho. Nothing else. They apparently don't care.

Further, Altera's material explaining 3rd party EDA really needs to be more comprehensive and explanatory.