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Altera_Forum's avatar
Altera_Forum
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16 years ago

Using vho file with cadence tools

Hello, I am running into problems while trying to simulate a very simple design ( the design just consist of a vhd file generated by quartus to use a simple PLL ( one clock input, one clock ou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

ok, I 've tried the example from altera and it seems to work well... ( multiplier ) They are using verilog model, so I have compiledmy design another time to generate a verilog output( .vo) and created a verilog testbench, but no way I can make working the PLL...

Did anyboby have tried this before?

Maybe the PLL behaviour has a issue... need some help!