Using Verilog parameters across incremental compilation partitions

Thanks for the replies. I am new to using incremental compilation, so I'm still trying to figure out what works and what doesn't.

That's exactly what I was wondering about, whether incremental would look at each partition separately, and as a result, use the default parameter value (specified in the "top-level" of the partition).

I looked at the Quartus handbook again, and according to 2-28 of volume 1, Quartus should detect module parameters in a higher-level module and add the higher-level module to the list of dependent files of a lower-level module that uses the parameters, so the partition can be recompiled when the parameters are changed.

When I look at the list of dependent files in my partitions from the analysis phase, this does not seem to be the case. None of the higher-level modules were included as a dependent file of a lower-level module. Files that were included using `include did make it to the dependency list though. I am not sure whether declaring the parameters in the Verilog2001 style has anything to do with it... I can try changing that.

The reason I need to do this is I would like to specify the parameter when I instantiate my component in SOPC builder, and that requires the parameter to exist in the top level of my design. The parameter is actually a CPU reset address, and I can tell the reset address is incorrect when I observe the CPU operation using signaltap.

Turning off incremental compilation did fix the problem with zero change to the source code... well at least I found what the problem is.