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Altera_Forum
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18 years ago

Using Verilog parameters across incremental compilation partitions

I am trying to compile a design that passes a Verilog (using the Verilog 2001 syntax of specifying parameters before ports) parameter down multiple hierarchies and partitions. The parameter is speci...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Incremental Compilation shouldn't change the functionality of your HDL. If you're passing a parameter down through your design hierarchy, it doesn't matter if it goes through partitions UNLESS you use the Post-Fit (Strict) netlist type, which ignores changes to source files and keeps prior fitting results.

Have you modified your design and now you're not seeing the correct behavior? How do you know the parameter doesn't take effect? When you ran quartus_map, did you see any messages indicating that your sub-partitions were resynthesized?

It could be a bug in the software. If you delete the project database and recompile (with Incremental Compilation), do you see the correct behavior?