Using Verilog and VHDL

Question

Hello!

I would like to ask if it is possible to use in a project both Verilog and VHDL files. For example: SDRAM controller in Verilog and State Machine in VHDL.

I'd really appreciate some help.

Michael C.

altera_forum · Answer

in Quartus, most certainly. for simulation you'll need to have a Simulator and license which supports mixed-languages. ModelSim-Altera Edition does not have this capability.

altera_forum · Answer

Thanks a lot for help:) All the best!

altera_forum · Answer

Use Modelsim SE

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Using Verilog and VHDL

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