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Altera_Forum's avatar
Altera_Forum
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16 years ago

Using Verilog and VHDL

Hello!

I would like to ask if it is possible to use in a project both Verilog and VHDL files. For example: SDRAM controller in Verilog and State Machine in VHDL.

I'd really appreciate some help.

Michael C.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    in Quartus, most certainly. for simulation you'll need to have a Simulator and license which supports mixed-languages. ModelSim-Altera Edition does not have this capability.