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I don't completely get what you're issue is, but one thing that is apparent is that the generated clocks for the mux were on the output port, not the output of the mux. I changed them to:
create_generated_clock -name {clk_A_mux}
-source [get_pins {inst19|altpll_component|pll|clk[0]}]
[get_pins {clk_mux|combout}]
create_generated_clock -name {clk_B_mux}
-source [get_ports {clk_B}]
[get_pins {clk_mux|combout}] -add
(Note that I added an LCELL after the clock mux, and called it clk_mux. This way the name of this combinatorial mux won't change compile-to-compile. Also note that a single LCELL doesn't add a level of logic. An LCELL just says this point is the output of a logic cell, and all the combinatorial logic can still be put into the LUT before it. You'd have to have two LCELLs to get an empty combinatorial node. I mention this since it's a common mis-perception.)
Anyway, without doing that, your CLK_B and CLK_A_POST_PLL both went through the mux and both fed inst13, etc. There was no way to have control and analyze paths from CLK_B to CLK_B_MUX without also analyzying between CLK_B and CLK_A_MUX. With this change you have that control.
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Thanks, that tells me where the problem lies. Actually, this is the first time I've used Quartus to produce a design, the real thing is in Mentor Graphics, but the parts shown are scaterred over half a dozen different entities so it was impratical to post it.
The reason for using the output port is that the muxes get absorbed into other logic in the process so I did the same in the example. I'll have to find a way to do something equivalent to your LCELL with Mentor.
I think I do still need the generated clock on the mux in order to specify the external setup and hold relationship between the clock and data pins but that's a separate task.
Thanks again for your help.
George
Honored Contributor
