Using the set_clock_groups command without hiding domain-crossing signals

I don't completely get what you're issue is, but one thing that is apparent is that the generated clocks for the mux were on the output port, not the output of the mux. I changed them to:

create_generated_clock -name {clk_A_mux}

-source [get_pins {inst19|altpll_component|pll|clk[0]}]

[get_pins {clk_mux|combout}]

create_generated_clock -name {clk_B_mux}

-source [get_ports {clk_B}]

[get_pins {clk_mux|combout}] -add

(Note that I added an LCELL after the clock mux, and called it clk_mux. This way the name of this combinatorial mux won't change compile-to-compile. Also note that a single LCELL doesn't add a level of logic. An LCELL just says this point is the output of a logic cell, and all the combinatorial logic can still be put into the LUT before it. You'd have to have two LCELLs to get an empty combinatorial node. I mention this since it's a common mis-perception.)

Anyway, without doing that, your CLK_B and CLK_A_POST_PLL both went through the mux and both fed inst13, etc. There was no way to have control and analyze paths from CLK_B to CLK_B_MUX without also analyzying between CLK_B and CLK_A_MUX. With this change you have that control.

(If you still want generated clocks on the output port, just add those in two, base them off of these two clocks, and be sure to use the -master_clock to specify which one it is based off of.)