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If you're relating logic clocked by the mux to other clock domains(or maybe the original clock domains, unmuxed), then you generally want to put multiple create_generated_clock assignments on the output of the mux. Now you have clock names for the original clock and the muxed version of each clock, and can usually create the proper groups that you want. If that's been tried and doesn't cover it, explain what you have and why it's not working, and maybe we can help more.
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Creating groups as you suggest is exactly what I am attempting to do. It started getting messy when I tried to explain the details so I've created an example project which is attached. It has for example one 'and' gate and one 'or' gate representing around 20,000 logic elements each. The real data mux has 8 channels, 32 bits wide from 3 clock domains domains but this example is as simple as I can make it and still be representative of the problem. The real data includes busses which obviously can't have different delays on the bits hence I need to constrain the data path through the mux for all clocks. I haven't bothered constraining the input and output ports in the example but they are done in the real design.
The core design includes a simple SDC file, TQ_test.sdc including clock definitions, and a TCL script that can be run to produce various reports. Then there's another SDC file, TQ_fix_mux.sdc, which can be read manually. It contains both the cross-domain commands for genuine signals and also the clock group commands intended to remove the spurious violations caused by muxing the clocks. It improves the performance but leaves two deliberate errors on the setup from inst16 to inst13 and the hold from inst14 to inst13. These are the sort of warnings I want to keep because I need to investigate and either adjust the constraints or the design to ensure data is passed accurately. The violations shown from inst13 to inst10 using different launch and latch clocks are the ones I want to get rid of.
Thanks for your help, it is much appreciated.
George
Honored Contributor
