Forum Discussion
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- Hi pletz, I´m not sure I fully understand. I am using VHDL, but is a .vqm file only for verilog? Also I have specified synplify pro as the synthesis tool in EDA settings, so I´m not too sure why quartus refers to it as "none". --- Quote End --- Hi Ardni, SynplifyPro is doing the synthesis of your vhdl and generates a netlist for Quartus with the extension <>.vqm. This <>.vqm ( it is a verilog netlist) is the design file which you need for quartus. You should setup the Quartus project by yourself. As long as the native flow doesn't work you can't trust that the setting from Synplify Pro are propagate to Quartus correct. Synplify Pro generates some tcl scripts which helps you to setup the Quartus project. I have a small project attached.