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Altera_Forum's avatar
Altera_Forum
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11 years ago

Using SPI on Qsys

Hi,

I want to use a DEO NANO FPGA to send a stream of data to an external device (a DDS). I want to use the SPI core Qsys. My address word is 8 bit long and then the data I have to send is 32bits long. The DDS has four pins for this. SDIO (bidirec for data in/out), SDO (out from DDS), sclk (for latching onto the data) and csb (to decide whether data should be latched onto or not). I wanted to use Qsys to use a clock, the nios processor, a memory. JTAG (to connect to computer) and the SPI core. I basically had the Qsys tutorial to refer to where they use Qsys with switches and LEDs. From the tutorial I see that the Qsys generated file is called to the main module.Something as follows:

ddstalk NiosII(

.clk_clk(CLOCK_50),

.reset_reset_n(1'b1),

.spi_MISO(sdio),

.spi_SCLK(sclk),

.spi_MOSI(sdo),

.spi_SS_n(q));

What I don't understand is where I can store my data that has to be sent to the DDS from the FPGA. Do I have to change something in the verilog code generated by Qsys or do I just call some other parameter into this module? It would be great if someone had a verilog example of how to use SPI. Or a code for SPI itself and how it is implemented. Thank you very much!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You mention Qsys - can I assume you're using a Nios? Where does the Nios code execute from? The external SDRAM?

    Assuming so, you'd put an appropriate data array in your software - which would result in your data being stored in the SDRAM.

    If you're not using a Nios then you need to solve it another way, probably by instantiating a ROM in the FPGA and implementing a small state machine to read the data from ROM and throw it at the SPI interface.

    A little more project detail will be helpful.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi Alex,

    Yes, I am using NIOS. I think my nios code executes from the on chip ram/rom (as I said, I was following the Altera tutorial). But I'm not too sure if I'm right (I'm quite new to quartus, verilog and anything to do with an FPGA). I've attached a screenshot of the Qsys page. If I am using the onchip ram/rom, how do I write this data to it?

    My project basically is to use the parallel ports of the DDS to modulate phase. But before that I have to write data to some of the registers on the DDS. This can only be done using SPI. The first 8 bits will be the address of the data register to address and the next 40 bits will be the data itself. After I have sent this information, I don't need to use the SPI anymore and will switch to the parallel mode communication. So basically I need SPI only to initialize the parameters on the DDS. I hope this helps. And once again, thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Read the SPI section in the embedded peripheral ip user guide (http://www.altera.com/literature/ug/ug_embedded_ip.pdf) - see section 10.

    You need to write to the 'txdata' register to send commands to your slave device. This will amount to a number of function calls from your software. So, the data you wish to send will be embedded in your code, thus will end up in whatever memory your software executes from (you don't specifically need to provision the data into that memory). Yes, from what I can see of your Qsys image, it looks like you're running from on-chip memory.

    So, to send the 8-bit address (1-byte) plus a further 5 bytes, this (probably) amounts to 6 function calls writing to the txdata register (depending on how your SPI interface peripheral is configured). This should result in the SPI access you're after. Note: make sure you understand the use of the 'TRDY' bit in the status register - you can't just fire 6 bytes at the txdata register.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi Alex,

    Thanks for the help. So as I had mentioned in my first post, the Qsys file is called to the main module. How would I call a function to my main module from a qsys module? From what I see in the link you sent me (and other places) I have to use HAL to call the functions. But can this be integrated into my verilog code? Thanks!