Using Signal Tap

1) The design you put into the FPGA captures data on the inputs and writes data to outputs, so it's already doing what you want(assuming your design is correct). You're not trying to detect this data, but somehow get it to a monitor so you can look at it.

2) SignalTap should work, although you don't want to probe the actual I/O. Your design most likely has registers at the I/O(good design practive) and those should get placed in the I/O cell. If you SignalTap the actual I/O, another register gets added, which can't be placed in the I/O cell and will have different timing, so it will be looking at the data differently then what you're actually reading/writing. Instead you generally want to look at what comes out of the input registers(what you've just read in), and what you're putting into the output registers(what you're about to write out.)

3) SignalTap is actually considered a debug tool, to capture signals internal to the FPGA. Most designs, when they're done, don't have signaltap in them.

4) If you really want to look at what's going into/out of the FPGA, then a logic analyzer is probably the tool you want to use.

5) You can also design your own interface. If a user really needs some sort of interface between the FPGA and a computer, than they often do that, but it's not trivial. Nios II/SOPC Builder have peripherals that can do this.