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Altera_Forum
Honored Contributor
17 years agoI understand, that you wan to implement a ternary signal. It's not directly provided by verilog, but could be emulated by two binary (std_logic) signals respectively a two-bit vector.
I understand, that you wan to implement a ternary signal. It's not directly provided by verilog, but could be emulated by two binary (std_logic) signals respectively a two-bit vector.