Honored Contributor
Honored ContributorQuartus only generates Verilog for these bits of IP. However, by selecting VHDL it also generates a VHDL prototype which you can instantiate in your code. Providing you compile your libraries ModelSim will allow you to effectively perform a mixed language simulation. So, no. You don't need to learn Verilog.
Refer to Altera's "modelsim tcl scripting examples (https://www.altera.com/support/support-resources/design-examples/design-software/tcl/tcl-modelsim.html)" for details on using the Altera libraries for simulation. The scripts encompass libraries for all devices - you can strip out what you don't need. Cheers, Alex
