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Altera_Forum
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9 years ago

Using QDR II+ IP core in Quartus Prime 16.1 project

Hi, I am new to Altera and also new in this company which uses Altera (Stratix V dev boards), so I have to adapt. And I have a couple of questios: I have installed Quartus Prime 16.1 on Wi...
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Altera_Forum
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9 years ago

Quartus only generates Verilog for these bits of IP. However, by selecting VHDL it also generates a VHDL prototype which you can instantiate in your code. Providing you compile your libraries ModelSim will allow you to effectively perform a mixed language simulation. So, no. You don't need to learn Verilog.

Refer to Altera's "modelsim tcl scripting examples (https://www.altera.com/support/support-resources/design-examples/design-software/tcl/tcl-modelsim.html)" for details on using the Altera libraries for simulation. The scripts encompass libraries for all devices - you can strip out what you don't need.

Cheers,

Alex