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Altera_Forum
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8 years ago

Using QDR II+ IP core in Quartus Prime 16.1 project

Hi,

I am new to Altera and also new in this company which uses Altera (Stratix V dev boards), so I have to adapt. And I have a couple of questios:

I have installed Quartus Prime 16.1 on Windows 10 and I tried following this instruction for QDR core (Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide), but I got the following problems:

1. All the menus are completely different. Eg, there are not these steps "Parameterize" where it says to chose memory type, clock speed etc.

2. I can not find my memory in the Presets list in the Mega Wizards menu. That is not such a problem, since I can find all timings in the data sheet, but there are some options which I don't understand and it is not explained in the instruction. Can you offer a pdf tutorial for Mega Wizard?

3. I don't understand why the code is generated in Verilog when I marked VHDL (that is the biggest problem). I would like to extract just the SRAM controller (Avalon to AVL) and use it in my simulation and later board. Is it possible to do that without learning Verilog? Can the IP be generated COMPLETLY on VHDL?

Thank you,

Ivan Mitic

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Quartus only generates Verilog for these bits of IP. However, by selecting VHDL it also generates a VHDL prototype which you can instantiate in your code. Providing you compile your libraries ModelSim will allow you to effectively perform a mixed language simulation. So, no. You don't need to learn Verilog.

    Refer to Altera's "modelsim tcl scripting examples (https://www.altera.com/support/support-resources/design-examples/design-software/tcl/tcl-modelsim.html)" for details on using the Altera libraries for simulation. The scripts encompass libraries for all devices - you can strip out what you don't need.

    Cheers,

    Alex