Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Using PLL "lock" signal as the async reset in Verilog

If I want to use the PLL "lock' signal to work as an async reset, the "lock" signal will keep low after the FPGA is powered and goes high after a duration. If I won't reset my PLL, then it means "loc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

--- Quote Start ---

Would this be the 'initial' block?? Or is there something else?

--- Quote End ---

Synthesis tools do not support initial blocks very consistently. If you want to have an FPGA power-up with a particular value in a register you can assign that value during the initialization of the signal. For example;

logic [31:0] regA = 32'h12345678;

signal regA : std_logic_vector(31 downto 0) := X"12345678";

You can chose to override these values in the reset part of a clocked process.

Cheers,

Dave