Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorUsing PLL "lock" signal as the async reset in Verilog
If I want to use the PLL "lock' signal to work as an async reset, the "lock" signal will keep low after the FPGA is powered and goes high after a duration. If I won't reset my PLL, then it means "loc...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The negedge statement is so the Verilog understands you are using the signal as an asynchronous reset. It does not matter if there actually is a negedge. This is synthesizeable - it tells the compiler what the initial register state is in the download bit-stream. Cheers, Dave --- Quote End --- Thanks very much, Dave.
