Using PLL "lock" signal as the async reset in Verilog

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if there is only low voltage level in "lock", there is no falling edge, whether this lock signal can still trigger the reset or not?

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If you use lock as an active-low reset, and it never goes high, then your logic will remain in reset.

Conversely, if you have an active low reset signal, eg., rstN, and it never goes low, the reset condition will never occur. You will see this in simulation, in that a signal will never take on its reset value, but instead will take on the default value for the data type used in the process. In VHDL you can write something like this to set the "power-on" default condition for a signal

signal q : std_logic := '0'; -- power-on condition 
signal rstN : std_logic := '1'; -- never asserts low
process(clk, rstN)
begin
  if (rstN = '0') then
      q <= '0';  -- never occurs
  elsif rising_edge(clk) then
      q <= d;
  end if;
end process;

Verilog will have a similar construct.

Cheers,

Dave