Using PLL "lock" signal as the async reset in Verilog

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You do not want to use PLL lock as a reset signal directly. Not all PLL locked outputs have a debounce/deglitch filter, so they may toggle for a while before they stay in a static state.

Download the code associated with this PCIe test

http://www.alteraforum.com/forum/showthread.php?t=35678

There's a deglitch/debounce filter in there you can use to "clean-up" the locked signal. You can then decide whether to use the "clean" signal as a synchronous or asynchronous reset signal.

Cheers,

Dave

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Hi Dave,

Thanks very much to mention this. I will be very careful to use the lock of PLL as the reset.

I still want to be clear about my question. Let's assume the lock from PLL is a clean signal. Can I write the verilog code as my previous post?

Thanks very much.