Using ModelSim to simulate ROM (hex file initalized)

Any thoughts? Here is a pared down version of my code if that helps. I tried to make sure it wasn't synthesizing anything away, by tying some of the input to switches and tying output to LEDs.

module Project(SW, answer, LEDR, LEDG, KEY);
parameter granularity = 9;
input SW;
input KEY;
output answer;
output  LEDR;
output LEDG;
wire clock, clock1;
wire result;
wire data1;
reg data2;
wire qout
reg ready;
reg signed  Dx1, Dy1, Dz1, Ex1, Ey1, Ez1, Fx1, Fy1, Fz1;
reg signed  Dx2, Dy2, Dz2, Ex2, Ey2, Ez2, Fx2, Fy2, Fz2;
reg counter, lagcounter;
always @(posedge clock or negedge KEY) begin //or negedge KEY
if(~KEY)begin
data2  <= {16{1'b0}};
Dx1 <= 3;
Dy1 <= 4;
Dz1 <= 1;
Ex1 <= 5;
Ey1 <= 3;
Ez1 <= 1;
Fz1 <= SW;
Fx1 <= SW;
Fy1 <= SW;
Dx2 <= 1;
Dy2 <= 1;
Dz2 <= 1;
Ex2 <= 2;
Ey2 <= 1;
Ez2 <= 10;
Fx2 <= 1;
Fy2 <= 2;
end
else begin
Dx1 <= Dx2;
Dy1 <= Dy2;
Dz1 <= Dz2;
Ex1 <= Ex2;
Ey1 <= Ey2;
Ez1 <= Ez2;
Fx1 <= Fx2;
Fy1 <= Fy2;
Dx2 <= Dx1;
Dy2 <= Dy1;
Dz2 <= Dz1;
Ex2 <= Ex1;
Ey2 <= Ey1;
Ez2 <= Ez1;
Fx2 <= Fx1;
Fy2 <= Fy1;
end
end
always @(posedge SW) begin
case(lagcounter)
//0: data2  <= qout;
0: begin data2  <= qout; ready <= 0; end
1: data2  <= qout;
2: data2  <= qout;
3: data2  <= qout;
4: data2  <= qout;
5: data2  <= qout;
6: data2  <= qout;
7: data2  <= qout;
8: data2  <= qout;
9: data2  <= qout;
10: data2  <= qout;
11: data2  <= qout;
12: data2  <= qout;
13: data2  <= qout;
14: data2  <= qout;
15: ready <= 1;
endcase
end
always @(posedge SW or negedge KEY) begin
if(~KEY)begin
counter <= 0;
end
else begin
counter <= counter + 1;
lagcounter <= counter;
end
end
assign clock = SW;
assign clock1 = SW;
submodule test1(.Dx(Dx1), .Dy(Dy1), .Dz(Dz1), .Ex(Ex1), .Ey(Ey1), .Ez(Ez1), .Fx(Fx1), .Fy(Fy1), .Fz(Fz1),
.check(result), .clock(clock), .data(data2), .loadenable(ready));	
rom_mem pointdata(
.address(counter),
.clock(~clock1),
.q(qout));
assign LEDG = (~answer) && ready;
assign LEDG = result && ready;
endmodule