Using ModelSim-Altera with Altera designs

Hello,

the 'U'|'X'|... is an everydays ModelSim issue. In many cases,it simply indicates that a signal isn't initialized. If you have e. g. a clock dividing counter, you will never see a clock output from this counter unless you initialize it either explicitely (e. g. during reset) or add a power on default to the signal definition. This is apparently different from real life FPGA behaviour, but is necessary to discover all possible uncertainties in FPGA code, I think. Also the behaviour regarding INOUT signal's initial state is different. With ModelSim you need an explicite initialisation to 'Z', otherwise an uninitialized INOUT could drive the bus to 'X', Quartus in contrast assumes 'Z' as default.

Regards,

Frank