Honored Contributor
Honored ContributorI see two aspects of your question
- the VHDL syntax part - speed (the real problem) The first point is rather trivial. Component instantiations are only allowed in concurrent code, not in sequential blocks. I don't apply to retell the basic VHDL concepts in this post, you should review the topic in your favourite VHDL text book. But it's a more formal point because you can place the divider outside the block and "connect" it through signals. Synchronizing a piplined divider needs to be considered as additional problem, but is basically possible. For signed and unsigned types, inference of hardware dividers from a "/" division operator is also supported by the compiler. But you have only limited options to control pipelined operation, so it may be better to refer to explicite MegaFunction instantiation. If pipeline operation is necessary is mainly a matter of your clock speed. Timing analysis will answer the question. A more general question is, if you actually need a divider for your design?
