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Altera_Forum's avatar
Altera_Forum
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13 years ago

using integer

Hi, I have two questions about using integer in VHDL. 1. If I had to convert a std_logic_vector to an integer, is it better to use CONV_INTEGER(MyVector) or to_integer(unsigned(MyVector)) ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Ok, that means to_integer(unsigned(slv_value)) is standardised and CONV_INTEGER(MyVector) isn't.

Right?