Using `define constant for decoding address busses

Hi,

I am trying to make a list of addresses in my project to be use throughout all of my Verilog modules.

I have created a "addr.vh" file to put the addresses in as follows:

addr.vh

`ifndef _addr_vh_

`define _addr_vh_

`define M 'h01808;

`endif

In a module I trying to store some data when the chip select, write signal and address are true in the

follow code:

always @ (posedge fpga_clk)

begin

if (reset_low_sync == false)

begin

motor_dis_reg <= 'h0000;

end

else if ((!fpga_cs_low & !rw_low) & (addr == `M))

begin

motor_dis_reg <= data_in;

end

end

I keep getting a syntax error# 10170 where I am doing the address comparison with the `M statement.

The logic works fine if put the true constant value " 'h01804" instead of the `define M. I though the `define

was a one for one substitution? Is this use of `define macro not legal??

Thank you for any reading and any help you may provide!

Larry