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SS5's avatar
SS5
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Using AVALON FIFO MEMORY CORE : Data are Repeating in NIOS

Hello, I am generating Trigger (500ns) and Counter data using Verilog code, whereas at every positive edge of trigger i am collecting and storing the data in register. Verilog code module Coun...
Ahmed_H_Intel1's avatar
Ahmed_H_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hello,

Can you please review this part of code:

  1. always@(posedge clk)
  2. begin
  3. if(reset)
  4. begin
  5. trig<=0;
  6. temp<=0;
  7. counter_out<=0;
  8. end
  9. else if (enable==1'b1)
  10. begin
  11. counter_out<=counter_out+1;
  12. temp<=temp+1;
  13. if(temp==25)
  14. begin
  15. temp<=0;
  16. trig<=~trig;
  17. end
  18. end
  19. end

I see that after the first count is over if the reset signal didn't come the trig will stay high and there will be two counters are counting at the same time because (assign temp1=trig;) temp1 will be high and then the next counter will be enabled and counting with the clk

  1. always@(posedge temp2)
  2. if(reset)
  3. counter_result<=0;
  4. else
  5. begin
  6. counter_result<=counter_result+1;
  7. end
  8. always@(posedge trig)
  9. if(reset)
  10. Final_value<=0;
  11. else
  12. begin
  13. Final_value<=counter_result;
  14. end

I recommend to remove this assignment and try again

assign temp2=temp1&&clk;

or to change it to

assign temp2=temp1;

I know this isn't the desired system but just for debugging