New ContributorThere is a large Quartus II project, consisted of a multiple bdf, verilog, VHDL files. Is it possible to compile it into some single file (verilog or VHDL or some other), and then use it as a single "black box" module for other projects, without showing its internall structure?
Regular ContributorHello,
This should be possible. You may find these pages useful:
And since you are using Quartus II you should be able to create VHDL/Verilog file from .bdf file.
Does this answer your question?
Regards,
Nurina
Regular ContributorHello,
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Regards,
Nurina
