Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- for assignment a variable to an hardware component, for example an X input with key / sw is enough do for example: signal X: KEY[0] --- Quote End --- Not quite. There's two ways you could do something like this;
signal x : std_logic;
-- "Read" the state of key(0) into x
x <= key(0);
or the shorthand version
alias x is key(0);
Note: VHDL is case insensitive, so writing capitals makes no difference. A typical "convention" is to write generics in capitals, but even that is not universal. Cheers, Dave